3 Day Open Conference

Modern verification methods for airborne FPGA / ASIC designs
Tuesday 18th November 2008
15.00 - 15.20
Auditorium 2

Over the last decade, complexity of FPGA/ASIC designs has grown at an astounding rate. While designing these complex electronic devices is difficult, thoroughly verifying them can be close to impossible -- unless you are using some of the more modern methods that have evolved to address these challenges. Come to this session to get an overview of some of the more recent breakthroughs in verification technology, and learn which techniques might be most applicable to your FPGA/ASIC devices.

About the Speaker(s):

David Landoll
Verification Architect
Mentor Graphics, USA

David Landoll is responsible for performing advanced verification methodology audits, identifying inefficiencies, recommending and implementing improvements, and creating new methodologies, especially in the mil-aero industry and for those companies adopting Do-254. Previously, David held technical and management jobs at 0-In Design Automation, Synopsys, Amdahl and Honeywell Bull. He has a BSEE Cum Laude from the University of Arizona, and MBA Cum Laude from Santa Clara University.